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FEATURES 1% Total Accuracy 630 A Typical Quiescent Current Shutdown Current: 1 A (Typical) Stable with 10 F Load Capacitor 4.5 V to 15 V Input Operating Range Integrated Reverse Leakage Protection 6-Lead SOT-23-6 and 8-Lead SO-8 Packages Programmable Charge Current -20 C to +85 C Ambient Temperature Range Internal Gate-to-Source Protective Clamp APPLICATIONS Li-Ion Battery Chargers Desktop Computers Hand-Held Instruments Cellular Telephones Battery Operated Devices
SD
Lithium-Ion Battery Charger ADP3820
FUNCTIONAL BLOCK DIAGRAM
BIAS
+ - 50mV
VIN
IS VREF GATE VOUT
ADP3820
GND
GENERAL DESCRIPTION
The ADP3820 is a precision single cell Li-Ion battery charge controller that can be used with an external Power PMOS device to form a two-chip, low cost, low dropout linear battery charger. It is available in two voltage options to accommodate Li-Ion batteries with coke or graphite anodes. The ADP3820's high accuracy ( 1%) low shutdown current (1 A) and easy charge current programming make this device especially attractive as a battery charge controller. Charge current can be set by an external resistor. For example, 50 m of resistance can be used to set the charge current to 1 A. Additional features of this device include foldback current limit, overload recovery, and a gate-to-source voltage clamp to protect the external MOSFET. The proprietary circuit also minimizes the reverse leakage current from the battery if the input voltage of the charger is disconnected. This feature eliminates the need for an external serial blocking diode. The ADP3820 operates with a wide input voltage range from 4.5 V to 15 V. It is specified over the industrial temperature range of -20C to +85C and is available in the ultrasmall 6-lead surface mount SOT-23-6 and 8-lead SOIC packages.
VIN +5V
RS 50m C1 10 F R1 10k + - IS VIN
NDP6020P
IO = 1A VOUT Li-Ion BATTERY
GATE VOUT
ADP3820-xx
SD GND
22 F
Figure 1. Li-Ion Charger Application Circuit
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
ADP3820-SPECIFICATIONS1(V
Parameter INPUT VOLTAGE OUTPUT VOLTAGE ACCURACY QUIESCENT CURRENT Shutdown Mode Normal Mode GATE TO SOURCE CLAMP VOLTAGE GATE DRIVE MINIMUM VOLTAGE
2
IN
= [VOUT + 1 V] TA = -20 C to +85 C, unless otherwise noted)
Symbol VIN Min 4.5 -1 Typ Max 15 +1 Units V %
Conditions
VIN = VOUT + 1 V to 15 V VSD = 2 V VSD = 0 V VSD = 2 V
VOUT
IGND IGND
1 630 6 0.7 1 80
15 800 10
A A V V mA dB
GATE DRIVE CURRENT (SINK/SOURCE) VGS GAIN V OUT CURRENT LIMIT THRESHOLD VOLTAGE LOAD REGULATION LINE REGULATION VIN - VIS IOUT = 10 mA to 1 A, Circuit of Figure 1 VIN = VOUT + 1 V to 15 V IOUT = 0.1 A Circuit of Figure 1 (No Battery) VIH VIL VSD = 0 V to 5 V VIN = Floating VSD ISD IDISCH
40 -10
75 +10
mV mV
-10 2.0
+10 0.4
mV V V A A
SD INPUT VOLTAGE SD INPUT CURRENT OUTPUT REVERSE LEAKAGE CURRENT
-15 3
+15 5
NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 2 Provided gate-to-source clamp voltage is not exceeded. Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V Enable Input Voltage . . . . . . . . . . . . . . . 0.3 V to (VIN + 0.3 V) Operating Ambient Temperature Range . . . . -20C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C JA, SO-8 Package . . . . . . . . . . . . . . . . . . . . . . . . 150C/W JA, SOT-23-6 Package . . . . . . . . . . . . . . . . . . . . 230C/W Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
*This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged.
Model ADP3820ART-4.1 ADP3820ART-4.2 ADP3820AR-4.1 ADP3820AR-4.2
Voltage Output 4.1 V 4.2 V 4.1 V 4.2 V
Package Option*
Marking Code
RT-6 (SOT-23-6) BAC RT-6 (SOT-23-6) BBC SO-8 SO-8
*SOT = Surface Mount Package. SO = Small Outline. Contact the factory for availability of other output voltage options.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3820 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-2-
REV. A
ADP3820
PIN FUNCTION DESCRIPTIONS PIN CONFIGURATIONS SO-8 RT-6 (SOT-23-6)
8
Pin Pin SOT-23-6 SO-8 1 2 8 7
Name SD GND
Function Shutdown. Pulling this pin low will disable the output. Device Ground. This pin should be tied to system ground closest to the load. Output Voltage Sense. This pin is connected to the MOSFET's drain and directly to the load for optimal load regulation. Bypass to ground with a 10 F or larger capacitor. Gate drive for the external MOSFET. Input Voltage. This is also the positive terminal connection of the current sense resistor. Current Sense. Used to sense the input current by monitoring the voltage across the current sense resistor. It is connected to the more negative terminal of the resistor as well as the power MOSFET's source pin. IS pin should be tied to the VIN pin if the current limit feature is not used. No Connect.
IS 1 NC 2 SD GND SD 1 GND 2
6
IS
ADP3820
7
TOP VIEW GATE 3 (Not to Scale) 6 NC VIN 4
5
VIN TOP VIEW VOUT 3 (Not to Scale) 4 GATE
5
ADP3820
VOUT
NC = NO CONNECT
3
5
VOUT
4 5
3 4
GATE VIN
6
1
IS
2, 6
NC
REV. A
-3-
ADP3820 -Typical Performance Characteristics
4.110 VIN = 5.1V 0.740 OUTPUT VOLTAGE - V 4.105 0.760 I LOAD = 10mA
0.720
IGND - mA
0.700 0.680
4.100
0.660 4.095 0.640
4.090
0
200
400 600 ILOAD - mA
800
1000
0.620
5
7
9 11 INPUT VOLTAGE - V
13
15
Figure 2. V OUT vs. ILOAD (VIN = 5.1 V)*
Figure 5. IGND vs. VIN (I LOAD = 10 mA)*
4.110 I LOAD = 1A
0.900 ILOAD = 1A
OUTPUT VOLTAGE - V
4.105
0.850
4.100
IGND - mA 5 7 9 11 13 15
0.800
4.095
0.750
4.090
0.700
5
7
INPUT VOLTAGE - V
9 11 INPUT VOLTAGE - V
13
15
Figure 3. VOUT vs. VIN (ILOAD = 1 A)*
Figure 6. IGND vs. VIN (I LOAD = 1 A)*
4.110 I LOAD = 10mA
1.200 VIN = 5.1V 1.100
OUTPUT VOLTAGE - V
4.105
1.000 IGND - mA 5 7 9 11 13 15 0.900 0.800 0.700 0.600
4.100
4.095
4.090
0.500 0.001
0.1 ILOAD - mA
10
1000
INPUT VOLTAGE - V
Figure 4. VOUT vs. VIN (I LOAD = 10 mA)*
Figure 7. I GND vs. ILOAD (VIN = 5.1 V)*
*Reference Figure 1.
-4-
REV. A
ADP3820
1.100 VIN = 5.1V I LOAD = 10mA 1.000 4.190 0.900
OUTPUT VOLTAGE - V
4.230 4.210 VOUT = 4.2V
IGND - mA
4.170 4.150 4.130 VOUT = 4.1V 4.110
0.800
0.700
0.600 4.090 0.500 -40 4.070 -40
-20
0
20 40 TEMPERATURE - C
60
80
-20
0
20 40 TEMPERATURE - C
60
80
Figure 8. Quiescent Current vs. Temperature*
Figure 11. VOUT vs. Temperature, VIN = 5.1 V, ILOAD = 10 mA*
4.5 I LOAD = 10mA 4.0 3.5 OUTPUT VOLTAGE - V 3.0 PSRR - dB 2.5 2.0 1.5 1.0 0.5 0 0 1 2 3 4 5 4 3 INPUT VOLTAGE - V 2 1 0
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M CLOAD = 10 F I LOAD = 1mA
Figure 9. Power-Up/Power-Down*
Figure 12. Ripple Rejection*
INPUT VOLTAGE - V
5.000 7.0 5.5 OUTPUT VOLTAGE - V 4.000 ILOAD = 10mA COUT = 10 F VIN = 5.1V RS = 0.5
3.000
OUTPUT VOLTAGE - V
4.2 4.1
2.000
1.000 4.0 0.000
0
20
40
60 80 ILOAD - mA
100
120
140
Figure 10. Line Transient Response (10 F Output Cap)*
Figure 13. Current Limit Foldback*
REV. A
-5-
ADP3820
APPLICATION INFORMATION
The ADP3820 is very easy to use. A P-channel power MOSFET and a small capacitor on the output is all that is needed to form an inexpensive Li-Ion battery charger. The advantage of using the ADP3820 controller is that it can directly drive a PMOS FET to provide a regulated output current until the battery is charged. When the specified battery voltage is reached, the charge current is reduced and the ADP3820 maintains the maximum specified battery voltage accurately. When fully charged, the circuit in Figure 1 works like a well known linear regulator, holding the output voltage within the specified accuracy as needed by single cell Li-Ion batteries. The output is sensed by the VOUT pin. When charging a discharged battery, the circuit maintains a set charging current determined by the current sense resistor until the battery is fully charged, then reduces it to a trickle charge to keep the battery at the specified voltage. The voltage drop across the RS current sense resistor is sensed by the IS input of the ADP3820. At minimum battery voltage or at shorted battery, the circuit reduces this current (foldback) to limit the dissipation of the FET (see Figure 13). Both the VIN input and VOUT sense pins of the IC need to be bypassed by a suitable bypass capacitor. A 6 V gate-to-source voltage clamp is provided by the ADP3820 to protect the MOSFET gates at higher source voltages. The ADP3820 also has a TTL SD input, which may be connected to the input voltage to enable the IC. Pulling it to low or to ground will disable the FET-drive.
Design Approach
ADP3820. This k factor between VO of 0 V to about 2.5 V is: k ~ 0.65. JA = T/(IO x k x VIN ) = 100/(1 x 0.65 x 5) = 30.7C/W This thermal impedance can be realized using the transistor shown in Figure 1 when surface mounted to a 40 x 40 mm double-sided PCB with many vias around the tab of the surfacemounted FET to the backplane of the PCB. Alternatively, a TO-220 packaged FET mounted to a heatsink could be used. The or thermal impedance of a suitable heatsink is calculated below: < ( JA - JC) = 30.7 - 2 = +28.7C/W Where the JC, or junction-to-case thermal impedance of the FET can be read from the FET data sheet. A low cost such heatsink is type PF430 made by Thermalloy, with a = +25.3C/W. The current sense resistor for this application can be simply calculated: R S = VS /IO = 0.05/1 = 50 m Where VS is specified on the data sheet as current limit threshold voltage at 40 mV-75 mV. For battery charging applications, it is adequate to use the typical 50 mV midvalue. B. Nonpreregulated Input Voltage If the input voltage source is, for example, a rectified and capacitor-filtered secondary voltage of a small wall plug-in transformer, the heatsinking requirement is more demanding. The VINMIN should be specified 5 V, but at the lowest line voltage and full load current. The required thermal impedance can be calculated the same way as above, but here we have to use the maximum output rectified voltage, which can be substantially higher than 5 V, depending on transformer regulation and line voltage variation. For example, if VINMAX is 10 V JA = T/(IO x k x VINMAX) = 100/(1 x 0.65 x 10) = +15.3C/W The suitable heatsink thermal impedance: < JA - JC = 15.3 - 2 = 13.3C/W A low cost heatsink is Type 6030B made by Thermalloy, with a = +12.5C/W.
Lower Current Option A. Preregulated Input Voltage (5 V 10%)
Due to the lower efficiency of Linear Regulator Charging, the most important factor is the thermal design and cost, which is the direct function of the input voltage, output current and thermal impedance between the MOSFET and the ambient cooling air. The worse-case situation is when the battery is shorted since the MOSFET has to dissipate the maximum power. A tradeoff must be made between the charge current, cost and thermal requirements of the charger. Higher current requires a larger FET with more effective heat dissipation leading to a more expensive design. Lowering the charge current reduces cost by lowering the size of the FET, possibly allowing a smaller package such as SOT-23-6. The following designs consider both options. Furthermore, each design is evaluated under two input source voltage conditions. Regarding input voltage, there are two options: A. The input voltage is preregulated, e.g., 5 V 10% B. The input voltage is not a preregulated source, e.g., a wall plug-in transformer with a rectifier and capacitive filter.
Higher Current Option A. Preregulated Input Voltage (5 V 10%)
For the circuit shown in Figure 1, the required JA thermal impedance can be calculated as follows: if the FET data sheet allows a max FET junction temperature of TJMAX = 150C, then at 50C ambient and at convection cooling, the maximum allowed T junction temperature rise is thus, TJMAX - TAMAX = 150C - 50C = 100C. The maximum current for a shorted or discharged battery is reduced from the set charge current by a multiplier factor shown in Figure 13 due to the foldback current limiting feature of the
If lower charging current is allowed, the JA value can be increased, and the system cost decreased. The lower cost is assured by using an inexpensive MOSFET with, for example, a NDT452P in a SOT-23-6 package mounted on a small 40 x 40 mm area on double-sided PCB. This provides a convection cooled thermal impedance of JA = +55C/W, presuming many vias are used around the FET to the backplane. Allowing a maximum FET junction temperature of +150C, at +50C ambient, and at convection cooling the maximum allowed heat rise is thus 150C-50C = 100C. The maximum foldback current allowed: IFB = T/( x VIN ) = 100/(55 x 5) = 0.33 A Thus the full charging current: IOUTMAX = IFB/k = 0.5 A k is calculated in the above example.
-6-
REV. A
ADP3820
The current sense resistor for this application: R S = VS/IO = 0.05/0.5 = 100 m
FET Selection Gate-to-Source Clamp
The type and size of the pass transistor are determined by the threshold voltage, input-output voltage differential and load current. The selected PMOS must satisfy the physical and thermal design requirements. To ensure that the maximum VGS provided by the controller will turn on the FET at worst case conditions, (i.e., temperature and manufacturing tolerances) the maximum available VGS must be determined. Maximum VGS is calculated as follows: VGS = VIN - VBE - IOUTMAX x RS where IOUTMAX = Maximum Output Current = Current Sense Resistor RS ~ 0.7 V (Room Temperature) VBE ~ 0.5 V (Hot) ~ 0.9 V (Cold) For example: VIN = 5 V, and IOUTMAX = 1 A, VGS = 5 V - 0.7 V - 1 A x 50 m = 4.25 V If VGS < 5 V, logic level FET should be considered. If VGS > 5 V, either logic level or standard MOSFET can be used. The difference between VIN and VO (VDS) must exceed the voltage drop due to the sense resistor plus the ON-resistance of the FET at the maximum charge current. The selected MOSFET must satisfy these criteria; otherwise, a different pass device should be used. VDS = VIN - VO = 5 V - 4.2 V = 0.8 V The maximum RDS(ON) required at the available gate drive (VDR) and Drain-to-Source voltage (VDS) is: RDS(ON) = VDS/IOUTMAX From the Drain-to Source current vs. Drain-to-Source voltage vs. gate drive graph off the MOSFET data sheet, it can be determined if the above calculated RDS(ON) is higher than the graph indicates. However, the value read from the MOSFET data sheet graph must be adjusted based on the junction temperature of the MOSFET. This adjustment factor can be obtained from the normalized RDS(ON) vs. junction temperature graph in the MOSFET data sheet.
External Capacitors
A 6 V gate-to-source voltage clamp is provided by the ADP3820 to protect most MOSFET gates in the event the VIN > VGS allowed and the output is suddenly shorted to ground. This allows use of the new, low RDS(ON) MOSFETs.
Short Circuit Protection
The power FET is protected during short circuit conditions with a foldback type of current limiting that significantly reduces the current. See Figure 13 for foldback current limit information.
Current Sense Resistor
Current limit is achieved by setting an appropriate current sense resistor (RS) across the current limit threshold voltage. Current limit sense resistor, RS, is calculated as shown above. Proper derating is advised to select the power dissipation rating of the resistor. The simplest and cheapest sense resistor for high current applications, (i.e., Figure 1) is a PCB trace. However, the temperature dependence of the copper trace and the thickness tolerances of the trace must be considered in the design. The resistivity of copper has a positive temperature coefficient of +0.39%/C. Copper's Tempco, in conjunction with the proportional-toabsolute temperature ( 0.3%) current limit voltage, can provide an accurate current limit. Table I provides the typical resistance values for PCB copper traces. Alternately, an appropriate sense resistor, such as surface mount sense resistors, available from KRL, can be used.
Table I. Printed Circuit Copper Resistance
Conductor Thickness 1/2oz/ft2 (18 m)
Conductor Width/Inch 0.025 0.050 0.100 0.200 0.500 0.025 0.050 0.100 0.200 0.500 0.025 0.050 0.100 0.200 0.500 0.025 0.050 0.100 0.200 0.500
Resistance m /In 39.3 19.7 9.83 4.91 1.97 19.7 9.83 4.91 2.46 0.98 9.83 4.91 2.46 1.23 0.49 6.5 3.25 1.63 0.81 0.325
1oz/ft2 (35 m)
The ADP3820 is stable with or without a battery load, and virtually any good quality output filter capacitors can be used (anyCAPTM), independent of the capacitor's minimum ESR (Effective Series Resistance) value. The actual value of the capacitor and its associated ESR depends on the gm and capacitance of the external PMOS device. A 10 F tantalum or aluminum electrolytic capacitor at the output is sufficient to ensure stability for up to a 10 A output current.
Shutdown Mode
2oz/ft2 (70 m)
3oz/ft2 (106 m)
Applying a TTL high signal to the SD pin or tying it to the input pin will enable the output. Pulling this pin low or tying it to ground will disable the output. In shutdown mode, the controller's quiescent current is reduced to less than 1 A.
anyCAP is a trademark of Analog Devices, Inc.
REV. A
-7-
ADP3820
PCB Layout Issues
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
6-Lead Plastic Surface Mount Package RT-6 (SOT-23-6)
0.122 (3.10) 0.106 (2.70)
0.071 (1.80) 0.059 (1.50) PIN 1
6 1
5 2
4 3
0.118 (3.00) 0.098 (2.50)
0.037 (0.95) BSC 0.075 (1.90) BSC 0.051 (1.30) 0.035 (0.90) 0.006 (0.15) 0.000 (0.00) 0.057 (1.45) 0.035 (0.90) 0.020 (0.50) SEATING 0.010 (0.25) PLANE 10 0.009 (0.23) 0 0.003 (0.08) 0.022 (0.55) 0.014 (0.35)
8-Lead Narrow Body Package SO-8
0.1968 (5.00) 0.1890 (4.80)
8 5 4
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
45
0.0500 (1.27) 0.0160 (0.41)
-8-
REV. A
PRINTED IN U.S.A.
C2986a-2-9/99
For optimum voltage regulation, place the load as close as possible to the device's VOUT and GND pins. It is recommended to use dedicated PCB traces to connect the MOSFET's drain to the positive terminal and GND to the negative terminal of the load to avoid voltage drops along the high current carrying PCB traces.
If PCB layout is used as heatsink, adding many vias around the power FET helps conduct more heat from the FET to the backplane of the PCB, thus reducing the maximum FET junction temperature.

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